Neural Network Circuit Analyzer for Intelligent Test Point Insertion and Fault Coverage Optimization

Background

The rapid advancement in digital technologies has led to increasingly complex logical circuits in integrated systems. Traditional testing and verification methods, once sufficient for simpler designs, now face challenges due to the intricate nature of modern circuits, particularly when dealing with features like reconvergent fan-outs and varied gate types. As chip designs evolve, the industry urgently requires more robust approaches to ensure high fault coverage and reliability, as undetected faults can lead to significant system failures and costly recalls.

Current testing techniques often suffer from computational inefficiency and limited scalability. Conventional methods struggle with the high overhead of repetitive computations, redundant simulation vectors, and the inherent difficulties in standardizing diverse circuit structures for effective fault analysis. These approaches typically do not manage the complex interplay between controllability and observability across circuit segments, resulting in suboptimal fault prediction and prolonged test cycles. The limitations in accurately capturing fault propagation and variations in circuit behavior further exacerbate reliability issues and constrain the overall efficiency of the testing process.

Technology

This system employs a dual-phase approach—training and prediction—to optimize fault coverage in logical circuits. During the training stage, it develops an artificial neural network that ingests detailed circuit data including controllability, observability, and one-hot encoded gate types. It standardizes circuits to achieve uniform fan-in/fan-out structures, extracts pertinent sub-circuits, and applies probabilistic fault simulation while avoiding redundant evaluations. The prediction phase iteratively assesses circuit performance by forecasting coverage changes and judiciously placing test points, thereby accommodating both stuck-at and delay fault models. A user-friendly interface facilitates parameter adjustments and results analysis, ensuring smooth integration with diverse circuit design tools.

What differentiates this technology is its efficient computation; it calculates global circuit parameters only once per cycle. The method’s use of comprehensive input vectors, including levelized circuit data, markedly outperforms traditional strategies when dealing with complex reconvergent fan-outs. Furthermore, its ability to autonomously generate varied training data through DAG-to-circuit conversion underlines its adaptability. This blend of machine learning precision with strategic circuit standardization creates a robust platform for accurate and scalable circuit testing.

Benefits

• Enhanced fault coverage accuracy through the use of an ANN model to predict coverage changes.
• Reduced computational overhead by calculating circuit-wide metrics only once per test point insertion cycle.
• Improved handling of complex circuit structures via circuit standardization and targeted sub-circuit extraction.
• Flexible integration with various platforms, including software, FPGAs, and custom hardware.
• User-friendly interface allowing customizable optimization rules and easy result analysis.

Applications

• Automated fault coverage optimization
• Optimized test point insertion
• Accelerated fault simulation
• Real-time circuit analysis
• Efficient validation workflow

Additional info

A machine learning-based system optimizes fault coverage in digital circuits via intelligent test point insertion. It employs two phases: training, which builds an ANN using circuit data (controllability, observability, gate types) while standardizing architectures and performing targeted fault simulations, and prediction, which iteratively assesses candidate points based on simulated fault coverage improvements. Automated DAG-to-circuit conversion ensures diverse training data, enhancing both computational efficiency and detection accuracy for stuck-at and delay faults.