A multi-ring coupled ring oscillator architecture for generating low-phase-noise, multi-phase clocks and reducing reference spurs

Background

Ring oscillators and phase-locked loops (PLLs) are foundational components in modern electronic systems, particularly for generating and distributing clock signals in applications such as phased arrays, beamforming, passive mixing, N-path filtering, and interleaved data converters. The demand for multi-phase clock generation has grown with the increasing complexity and performance requirements of wireless and mixed-signal systems. Traditional ring oscillators, which do not use LC tanks, are favored for their compactness and ease of integration, but they have historically suffered from poor phase noise performance. As a result, the need for improved oscillator architectures that can deliver low phase noise and a large number of output phases, while maintaining scalability and efficiency, has become critical for enabling high-performance, area- and power-efficient frequency synthesis in advanced electronic applications.

Despite various enhancements, current approaches to ring oscillator-based PLLs face significant challenges. Conventional single-ring oscillators (SROs) exhibit a tradeoff between the number of output phases and phase noise: increasing the number of stages to generate more phases typically degrades phase noise and increases power consumption. Injection-locked PLLs (IL-PLLs) have been used to improve phase noise, but they are prone to reference spurs caused by timing mismatches and waveform distortion from injection pulses. These spurs, along with noise injected from tail currents and adjacent oscillator stages, limit the achievable spectral purity and reliability of the output signals. Existing solutions, such as N-path filters and various coupling schemes, have only partially addressed these issues, often at the expense of increased circuit complexity or limited scalability, leaving a gap for a more robust and scalable solution.

Technology

The multi-ring coupled ring oscillator (MRO) is an advanced oscillator architecture that integrates multiple individual ring oscillators, coupling them at their common mode nodes using capacitors or phase shifters. This coupling introduces specific phase shifts between the rings (such as 60° for three rings or 90° for two), which minimizes noise injection from tail currents and adjacent rings. As a result, the MRO achieves significantly improved phase noise performance and supports a much larger number of output phases compared to traditional single-ring oscillators. When used within an injection-locked phase-locked loop (IL-PLL), only the main ring receives the reference injection, while auxiliary rings are coupled but not directly injected, leading to reduced reference spurs at auxiliary outputs. The architecture is highly scalable, allowing for precise phase alignment and fine-tuning, and can generate a large number of non-overlapping output phases—ideal for applications requiring multiphase clocks, such as phased arrays, beamforming, and high-speed data converters.

What differentiates this technology is its ability to break the conventional tradeoff between phase noise and the number of output phases in ring oscillators. By leveraging phase-shifted coupling at the common mode nodes, the MRO suppresses both 1/f noise up-conversion and inter-ring noise injection, which are major limitations in traditional designs. This results in substantial phase noise reduction (up to 7 dB improvement demonstrated in prototypes) without sacrificing frequency or increasing power consumption. Furthermore, the selective injection scheme in IL-PLLs enables auxiliary outputs to maintain low phase noise while achieving reference spur suppression of at least 12 dB compared to conventional approaches. The design’s scalability and flexibility in phase selection, combined with its area- and power-efficiency and compatibility with standard CMOS processes, make it a compelling solution for next-generation wireless, mixed-signal, and frequency synthesis systems requiring low-jitter, inductor-less, multi-phase clock generation.

Benefits

• Significantly improved phase noise performance compared to single-ring oscillators (e.g., 7 dB reduction)
• Increased number of available output phases for multi-phase signal generation (e.g., tripling phases in a triple-ring design)
• Reduced reference spurs in injection-locked PLLs by selective injection and precise phase alignment
• Scalable architecture supporting any number of rings and differential gain stages
• Low power consumption suitable for high-frequency operation (e.g., 1–1.5 GHz range)
• Enhanced noise immunity by minimizing noise injection from tail currents and adjacent rings via phase-shifted coupling
• Area- and power-efficient design enabling inductor-less, low-jitter PLL implementations
• Supports coarse and fine phase tuning for precise injection timing and spur suppression

Applications

• Phased array radar systems
• Multi-phase clock generation
• Beamforming wireless communications
• High-speed data converters
• Low-jitter frequency synthesizers

Additional info

This apparatus integrates multiple ring oscillators, coupling them at common mode nodes with specific phase shifts. This minimizes noise injection from tail currents and adjacent rings, improving phase noise and increasing output phases. When deployed in injection-locked loops, selective reference injection into a main ring reduces reference spurs at auxiliary outputs while maintaining low phase noise. The architecture is scalable.